The present invention relates to microelectronic circuits, especially those which are capable of converting signals from one signaling protocol, e.g., from a pair of differentially transmitted signals, to another signaling protocol, such as a signaling protocol in which one or more single-ended signals are transmitted.
Microelectronic circuits of various types of required to convert certain signals that are transmitted in accordance with one signaling protocol into different signals that correspond to a different signaling protocol. The process of converting from one signaling protocol to another can be problematic, particularly when the change involves more than merely shifting the voltage levels of the signals between one voltage to another. Some signaling protocols produce single-ended CMOS logic or TTL logic-type signals which have rail-to-rail signal swings which are readily usable by complementary metal oxide semiconductor (“CMOS”) logic circuits or transistor-transistor-logic (“TTL”). However, such single-ended rail-to-rail signals are not well adapted for transmitting high switching rate signals and/or transmitting signals within noisy environments.
On the other hand, signaling protocols which transmit signals via a pair of complementary non-return-to-zero (“NRZ”) differential signals are well adapted for transmitting high switching rate signals through noisy environments, and for doing so while consuming less power than that needed by other signaling protocols to achieve a comparable signal-to-noise ratio. Differential signaling protocols are being used increasingly in high-speed serializer-deserializer circuits, for example, for transmitting signals from one semiconductor device chip which houses an integrated circuit to another such semiconductor device chip. One such differential signaling protocol is known as current mode logic (“CML”). In the current mode logic protocol, an information signal is transmitted on a pair of wires as a pair of reduced signal swing NRZ differential signals. As an example, the differential signals swing between opposite high and low signal levels which have voltage levels that are usually only a few tens of millivolts to a few hundred millivolts apart. For instance, in one example, when a first one of the two differential signals is at a high level of 800 mV, the second one of the two differential signals can be at a low level of 400 mV. The difference between the high and low levels at a receiving circuit can be even smaller, such as about 50 mV and 100 mV, resulting in a peak-to-peak signal swing of 100 to 200 mV.
When the information carried by the two differential signals changes, the two signals swing between their respective levels to the opposite levels so that the first differential signal is at the low level and the second differential signal is at the high level. The two differentially transmitted current mode logic signals are received and converted to a single-ended signaling protocol by applying the two signals to circuits such as inverter circuits which amplify a difference (voltage and/or current) between them and outputting a single-ended output signal.
However, heretofore, many difficulties remain unaddressed in the performance of this signal conversion process. One key problem has been converting differential signals in such manner to produce rail-to-rail signals that have duty cycles compatible with the circuits that consume the signals. When the consuming circuits operate at their best with rail-to-rail signals having a 50% duty cycle, signals having noticeably asymmetric duty cycles, e.g., 55%-45%, 65%-35% or worse, can lead to high bit error rates, or require the transmission rate of the data carried thereby to be lowered. U.S. Pat. No. 6,559,685 to Green (“the Green Patent”) and U.S. Pat. No. 5,920,217 to Mellot (“the Mellot Patent”) illustrate examples of signal converter circuits that fail to achieve 50% duty cycles.
On the other hand, U.S. Pat. No. 6,426,660 to Ho et al. (“the Ho et al. Patent”) describes a circuit designed to convert a clock signal from one frequency to another and achieve a 50% duty cycle. However, the circuitry applied to the task is cumbersome, requires a relatively large area of a semiconductor chip to implement and consumes much power.